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High-speed printed circuit board design is a process of balancing the circuit design requirements, device technologies, and fabrication materials and methodologies, to deliver a PCB that can transfer signals between the components, with integrity. This article describes the various options and settings that you configure in Altium Designer to successfully design your high-speed board.
Early in the design process, it is important to identify signals that might require impedance matching so that additional termination components can be included before the component placement process is complete.
Since output pins are typically low impedance and input pins are typically high impedance, termination components may need to be added to the design to achieve impedance matching. Altium Designer includes a signal integrity simulator that can be accessed during both the design capture and board layout phases of the design process, allowing both pre- and post-layout signal integrity analysis to be performed Tools » Signal Integrity.
The simulator is based on a Fast Reflection and Crosstalk Simulator, which produces very accurate simulations using industry-proven algorithms. Because both design capture and board design use an integrated component system that links schematic symbols to relevant PCB footprints, SPICE simulation models and signal integrity macro-models, signal integrity analysis can be run at the schematic capture stage prior to the creation of the board design.
When no board design is present, the tool allows you to set up the physical characteristics of the design, such as the desired characteristic trace impedance, from within the signal integrity simulator.
At this pre-layout stage of the design process, the signal integrity simulator cannot determine the actual length of particular connections so it uses a user-definable average connection length to make its transmission line calculations. By carefully choosing this default length to reflect the dimensions of the intended board, you can gain a fairly accurate picture of the likely signal integrity performance of the design. Nets with potential reflection problems can be identified and any additional termination components can be added to the schematic before proceeding to board layout.
The values of these components can then be further tuned once the post-layout signal integrity analysis has been performed. The Signal Integrity analysis engine helps identify nets with potential reflection issues. Note that measurements can be taken directly from the waveforms.
The Signal Integrity analysis engine installs as a System Extension. If it is not currently installed, click the Configure button to install it. High-speed design is the art of managing the flow of energy from one point on a circuit board to another point. As the designer, you need to be able to focus your attention and apply the design constraints onto a signal that travels from this point on the board to that point on the board. This signal you are focusing on is not necessarily a single PCB net though.
The signal might be one branch of A0 in a design that you intend to route in a T-branch topology, with the other branch of A0 being another signal you need to focus your attention on as well, and be able to compare the route lengths of these two signals. Or the signal might include a series termination component in its path which the PCB editor sees as one component and two PCB nets , and if that signal is in a differential pair, its length needs to be compared to the length of the other signal in that pair.
You can manage these requirements using a feature known as xSignals , where an xSignal is essentially a user-defined signal path. You select the source pad and the target pad in the workspace or in the PCB panel then right-click on either to define that signal path as an xSignal.
As well as interactively defining an xSignal by its start and end pads, you also can run the intelligent xSignals Wizard , whose heuristics will help you to quickly set up a large number of xSignals between the chosen components. These xSignals can then be used to target design rules to your high-speed signals. The software understands the structure of these xSignals; for example, calculating the overall length of multiple nets connected through a termination component, as well as the distance through that termination component.
The panel also provides feedback on the signal length, highlighting xSignals that are close to meeting yellow or failing to meet red the applicable design constraints. In the image below the xSignal lengths of the CLK1 differential pair are different in length by more than allowed by the applicable Matched Length design rule. The panel includes the Signal Length , which is an accurate point-to-point length. Traditional length inconsistencies, such as tracks within pads and stacked track segments, are resolved, and accurate via span distances are used to calculate the Signal Length.
Note the thin line; this indicates the signal path through a series component. The delay caused by the length of the pin within the device package is also supported, by defining the Pin Package Delay. Main article: Controlled Impedance Routing. Traditionally, board designers would define the widths and thickness of the routing by entering a dimension for the width and selecting a thickness of copper for that layer.
This was generally sufficient since you only needed to ensure that the current could be carried and the required voltage clearances were maintained. This approach is not sufficient for the high-speed signals in your design, for these you need to control the impedance of their routes. Controlled Impedance routing is all about configuring the dimensions of the routes and the properties of the board materials to deliver a specific impedance.
This is done by defining a suitable impedance profile, and then assigning that profile to the critical high-speed nets in the routing design rules. The Layer Stack Manager opens in a document editor, in the same way as a schematic sheet, the PCB, and other document types do. Once the layer properties have been configured, switch to the Layer Stack Manager's Impedance tab to add or edit single or differential impedance profiles.
Simbeor SFS is an advanced quasi-static 2D field solver based on Method of Moments, which has been validated by convergence, comparisons, and measurements. The Simbeor SFS engine supports all modern board structures and materials, including the use of polygons on signal layers as reference layers.
The routing impedance is determined by the width and height of the route, and the properties of the surrounding dielectric materials. Based on the material properties defined in the Layer Stack Manager , the required routing widths are calculated when each impedance profile is created.
Depending on the material properties, the width may change as the routing layer is changed. This requirement to changes widths as you change routing layers is automatically managed by the applicable routing design rule configured in the PCB Rules and Constraints Editor Design » Rules.
For most board designs, there will be a specific set of nets to be routed with a controlled impedance. A common approach is to create a net class or differential pair class that includes these nets, then create a routing rule that targets this class, as shown in the images below.
Normally you manually define the Min, Max and Preferred Widths, either in the upper constraint settings to apply them to all layers; or individually for each layer in the layer grid.
For controlled impedance routing you enable the Use Impedance Profile option instead, then select the required Impedance Profile from the dropdown. When this is done, the Constraints region of the rule will change. The first thing you will notice is that the available layers region of the design rule will no longer show all signal layers in the board, it will now only show the layers enabled in the selected Impedance Profile.
The Preferred Width values and diff pair gap will update to reflect the widths and gaps calculated for each layer. For single-sided nets, the routing width is defined by the Routing Width design rule.
When you choose to Use an Impedance Profile, the available layers and Preferred Widths are controlled by the selected profile. The routing of differential pairs is controlled by the Differential Pair Routing design rule. For a differential pair, the available layers, the Preferred Width and the Preferred Gap are controlled by the selected profile. There is a great deal of debate about corners in high-speed signal routes.
While it is agreed that the electrons will not fly off when they hit a degree corner, a traditional degree corner is wider across the corner diagonal, which does change the impedance of the route. Rounded or degree corners are preferred - both are standard features of the PCB editor's interactive router - and if needed degree corners can be mitered using the Convert Selected Tracks to Chamfered Path command.
Note that this command converts the selected track segments into a single region object. So how do you know what target impedance to select? This is normally driven by the characteristic source impedance of the logic family or technology being used. Remember, the lower the impedance the greater the current drain, the higher the impedance the more chance there will be EMI emitted, and the more susceptible that signal will be to crosstalk. This is not exactly correct due to the coupling that occurs between the pair, which becomes stronger as they become closer, reducing the differential impedance of the pair.
Main article: Layer Stack Management. The materials used for the layers in your board, their dimensions, and the number of and order that the layers are arranged, are all defined in the Layer Stack Manager. Here you configure the various layers that are needed to fabricate the final board including the copper signal and plane layers, the dielectric layers that separate the copper, the cover layers, and the component overlay.
All fabricated layers are defined in the Layer Stack Manager Stackup tab. Detailed information about the material properties that are entered in the Layer Stack Manager are included in the Layer Stack Table and also in the Layer Stack Legend placed in a Draftsman document.
You can also Save a layer stackup as a template in the Layer Stack Manager File menu , and Load that template into future designs. Main article: Defining the Via Types. As mentioned in the overview section of this article, vias affect the impedance of the signal routing and are a key consideration in high-speed design.
As well as the length, hole diameter, and via land area affecting the impedance that the signal sees, any unused portion of a via barrel can act as a stub, contributing to signal reflections. These via types are all supported in Altium Designer. Back drilling of unused via barrels is also supported, these are defined in the Layer Stack Manager's Back Drills tab Learn more about configuring the board for back drilling. All of the various types of vias that can be fabricated can be defined in the Via Types tab of the Layer Stack Manager.
Summarizing this study and other references, the following guidelines are given to help minimize the impact of vias:. The design of the vias is a key ingredient in the high-speed board design process. The possible layer-to-layer via connection options are dictated by the fabrication process chosen to achieve the layer stackup, which means you must choose the fabrication and drilling process as the via style and the layer stackup is being defined.
The feature supports back drilling from both sides of the board, and back drilled sites can be easily examined in the PCB panel, with the board displayed in 3D mode. Read more about Controlled Depth Drilling. A good quality return path is essential for each high-speed signal in the design. Whenever the return path deviates and does not flow under the signal route, a loop is created and this loop results in EMI being generated, with the amount being directly related to the area of the loop.
The first image is a plane layer split into 3v3 and 5v0 zones; the second image is a signal layer with a 3v3 polygon and a 5v0 polygon. Net colors have been assigned and highlighting enabled. There is general agreement that a ground plane should not be split unless there is a specific requirement for it and you understand how to define and manage it.
Instead, the components should be arranged to keep noisy components separate from quiet components, and to also cluster components by the supply rail that they use. To help with the task of visually checking the return paths, you can configure the display so you can more easily examine the return path under the critical route paths. Checking if signals travel over a split line as they traverse different voltage areas on the plane. The four highlighted nets cross a split in the VCC power plane, creating a split in the return path of those signals.
Your net s will stand out, and any splits or discontinuities that lie in the return path, such as split lines or blowouts created by through-hole pads and vias, will be easier to see.
Breaks or necks in the return path can be detected by the Return Path design rule. The Return Path design rule checks for a continuous signal return path on the designated reference layer s above or below the signal s targeted by the rule. The return path can be created from fills, regions, and polygon pours placed on the reference signal layer, or it can be a plane layer.
The return path layers are the reference layers defined in the Impedance Profile selected in the Return Path design rule. These layers are checked to ensure the specified Minimum Gap width beyond the signal edge exists along the signal's path. Add a new Return Path design rule in the High Speed rule category. The return path layers are defined in the selected Impedance Profile , the path width beyond the signal edge is defined by the Minimum Gap.
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